1. Field of the Invention
This invention relates to the field of integrated circuits. More particularly, this invention relates to a method of making integrated circuits and integrated circuits utilising local interconnect conductors.
2. Description of the Prior Art
It is known to make and provide integrated circuits formed from processes involving multiple stages of lithography, deposition, etching, implantation etc. Advances in these processes have permitted device geometries to reduce thereby increasing the circuit density achievable and reducing cost. Recent production geometries have used devices with feature sizes of 45 nm. Projected future devices are expected to have sizes of 32 nm followed by 22 nm. As these device geometries become smaller, it is becoming increasingly difficult to form the patterns on the integrated circuit during manufacture necessary to create the desired circuit elements. In particular, if it is desired to produce lithographic shapes (patterns) including non-rectilinear shapes, then the accuracy and reliability with which such shapes can be produced is a significant difficulty in producing such integrated circuits. Rectilinear shapes are easier to reliably form. However, it is difficult to make the required connections and circuits using only rectilinear shapes when producing a circuit cell library for forming integrated circuits.
Another factor limiting the density with which circuit elements may be formed upon an integrated circuit is illustrated with reference to FIGS. 1 and 2 of the accompanying drawings. FIG. 1 illustrates a transistor 2 formed using a diffusion region 4 within a substrate 5 over which are formed a gate electrode 6 (a polysilicon channel) separated by a gate insulator layer 8 from the diffusion region 4. A source connection conductor 10 and a drain connection conductor 12 serve to provide a source electrode and a drain electrode contacting the diffusion region 4. The gate electrode 6 is provided with a gate connection conductor 14. The source connection conductor 10, the drain connection conductor 12 and the gate connection conductor 14 all extend through an insulator layer 16 toward Metal1 layer connections 18, 20, 22.
When manufacturing the transistor 2 illustrated in FIG. 1 it would be normal to form the diffusion region 4 in the substrate 6 and then deposit the gate insulator layer 8 and the gate electrode 6 over the diffusion region 4. The insulator layer 16 would then be formed covering the gate electrode 16 and the diffusion region 4 before a source opening, a drain opening and a gate opening were etched through the insulating layer 16 to respectively reach the diffusion region 4 to provide the source access, the diffusion region 4 to provide the drain access and the upper surface of the gate electrode 6 to provide gate access. The source opening, the drain opening and the gate opening are then filled with connection conductor material, such as tungsten, in a deposition step. Subsequently the Metal1 connections 18, 20, 22 are formed over the source connection conductor 10, the drain connection conductor 12 and the gate connection conductor 14 so as to provide electrical connections to other portions of the integrated circuit concerned.
As illustrated in FIG. 1, the etch depth required in order to etch the source opening and the drain opening is significantly greater than the etch depth required to etch the gate opening. The etching process used to etch through the insulating layer 16 will remove material of the insulator layer, but will not remove the gate electrode 6 to any significant degree. Accordingly, providing the alignment of the gate opening is accurately over the gate electrode 6, then the etching of the gate opening will stop when it reaches the upper surface of the gate electrode 6. The etching of the source opening and the drain opening will continue until the surface of the diffusion region 4 is reached. However, if the alignment of the etching of the gate opening is not sufficiently accurate, it is possible that the gate opening may continue down the side of the gate electrode 6 and reach the diffusion region 4. In this case, when the gate connection conductor 14 is then deposited in the gate opening, it will create a short circuit past the gate insulator layer rendering the transistor 2 non operative. It will be appreciated that in a modern integrated circuit containing many millions of transistors, if only a few of these transistors are incorrectly formed, then the entire integrated circuit may not function properly. Accordingly, the alignment of the gate opening over the gate electrode 6 is a source of failure which is conventionally addressed by the arrangement illustrated in FIG. 2. FIG. 2 illustrates a plan view of the transistor 2 shown in FIG. 1. As is illustrated in FIG. 2, the gate opening and the subsequently formed gate connection conductor 14 are offset so that they do not overlie the diffusion region 4. Thus, any misalignment in the etching of the gate opening may cause an excessively deep gate opening to be formed, but this gate opening will not reach the diffusion region 4 and accordingly cannot cause a short circuit past the gate insulating layer 8. Thus, a common design rule when forming circuit cells for integrated circuits is that the gate opening where the gate connection will be formed must not overlie the diffusion region 4. Whilst this approach avoids the short circuit problem discussed above, it reduces the density achievable for circuit elements within the final integrated circuit.